The Process and Stress-Induced Variability Issues of Trigate CMOS Devices

dc.citation.woscount	0	en_US
dc.contributor.author	Chung, Steve S.	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2017-04-21T06:50:00Z
dc.date.available	2017-04-21T06:50:00Z
dc.date.issued	2013	en_US
dc.description.abstract	Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the hot carrier stress induce the V-th variations. This paper will address the importance of these effects and the experimental demonstration of the process-and trap-induced fluctuations. The boron clustering, sidewall roughness, and the electrical stress effects can all be justified by the theory and the method. This method provides us a valuable tool for the understanding of the process and stress induced variability in 3D devices (e.g., FinFET).	en_US
dc.identifier.isbn	978-1-4673-2523-3	en_US
dc.identifier.journal	2013 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/136158
dc.identifier.wosnumber	WOS:000380585600151	en_US
dc.language.iso	en_US	en_US
dc.subject	Trigate CMOS	en_US
dc.subject	Variability	en_US
dc.subject	Variation	en_US
dc.subject	Reliability	en_US
dc.title	The Process and Stress-Induced Variability Issues of Trigate CMOS Devices	en_US
dc.type	Proceedings Paper	en_US

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