Full current-mode techniques for high-speed CMOS SRAMs

dc.citation.epage	582	en_US
dc.citation.spage	580	en_US
dc.contributor.author	Wang, SM	en_US
dc.contributor.author	Wu, CK	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.date.accessioned	2014-12-08T15:26:37Z
dc.date.available	2014-12-08T15:26:37Z
dc.date.issued	2002	en_US
dc.description.abstract	This paper describes an experimental 32Kx8 CMOS SRAM with a 9ns access time at a supply voltage of 3V using a 0.35um 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28mA at 100MHz under typical conditions.	en_US
dc.identifier.isbn	0-7803-7448-7	en_US
dc.identifier.journal	2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18918
dc.identifier.wosnumber	WOS:000186328300146
dc.language.iso	en_US	en_US
dc.title	Full current-mode techniques for high-speed CMOS SRAMs	en_US
dc.type	Proceedings Paper	en_US

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