A 1.2V Interference-Sturdiness, DC-Offset Calibrated CMOS Receiver Utilizing a Current-Mode Filter for UWB

dc.citation.epage	344	en_US
dc.citation.spage	341	en_US
dc.contributor.author	Shih, Horng-Yuan	en_US
dc.contributor.author	Chen, Wei-Hsien	en_US
dc.contributor.author	Juang, Kai-Chenug	en_US
dc.contributor.author	Yang, Tzu-Yi	en_US
dc.contributor.author	Kuo, Chien-Nan	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:03:56Z
dc.date.available	2014-12-08T15:03:56Z
dc.date.issued	2008	en_US
dc.description.abstract	An interference-sturdiness receiver with a current-mode filter for 3-5GHz UWB applications is implemented in a 1.2V 0.13 mu m CMOS process. The chip provides a maximum voltage gain of 70dB and a dynamic range of 60dB. The measured in-band OIP3 is +9.39dBm, out-of-band IIP3 -15dBm and noise figure 6.8dB in the maximum gain mode. An algorithm for the automatic digital DC offset calibration is also demonstrated.	en_US
dc.identifier.isbn	978-1-4244-2604-1	en_US
dc.identifier.journal	2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/2452
dc.identifier.wosnumber	WOS:000265155300086
dc.language.iso	en_US	en_US
dc.title	A 1.2V Interference-Sturdiness, DC-Offset Calibrated CMOS Receiver Utilizing a Current-Mode Filter for UWB	en_US
dc.type	Proceedings Paper	en_US

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