A New VLSI 2-D Fourfold-Rotational-Symmetry Filter Architecture Design

dc.citation.epage	96	en_US
dc.citation.spage	93	en_US
dc.contributor.author	Chen, Pei-Yu	en_US
dc.contributor.author	Van, Lan-Da	en_US
dc.contributor.author	Reddy, Hari C.	en_US
dc.contributor.author	Lin, Chin-Teng	en_US
dc.contributor.department	資訊工程學系	zh_TW
dc.contributor.department	Department of Computer Science	en_US
dc.date.accessioned	2014-12-08T15:19:53Z
dc.date.available	2014-12-08T15:19:53Z
dc.date.issued	2009	en_US
dc.description.abstract	In this paper, we propose two new two-dimensional (2-D) IIR and FIR filter architectures for 2-D transfer function using fourfold rotational symmetry. The presented type-I structure with fourfold rotational symmetry has the lowest number of multipliers, and zero latency. Importantly, the proposed type-II IIR filter possesses high speed, local broadcast, and the same number of multipliers and latency as the type I shows at expense of a slight increment of number of delay elements.	en_US
dc.identifier.isbn	978-1-4244-3827-3	en_US
dc.identifier.journal	ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/14100
dc.identifier.wosnumber	WOS:000275929800024
dc.language.iso	en_US	en_US
dc.title	A New VLSI 2-D Fourfold-Rotational-Symmetry Filter Architecture Design	en_US
dc.type	Proceedings Paper	en_US

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