Scheduler design issues for wireless high-speed data systems
| dc.citation.epage | 298 | en_US |
| dc.citation.spage | 293 | en_US |
| dc.citation.woscount | 0 | en_US |
| dc.contributor.author | Huang, CY | en_US |
| dc.contributor.author | Su, HY | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2019-04-02T06:04:42Z | |
| dc.date.available | 2019-04-02T06:04:42Z | |
| dc.date.issued | 2004-01-01 | en_US |
| dc.description.abstract | To understand the tradeoff between the system throughput and the user fairness, in this paper, two different scheduler design concepts are discussed and evaluated based on the full-buffer data model and finite packet-call-size data model. In finite packet-call-size data model, we will show analytically and by simulation that the system throughput depends on the number of active users and the user's in-slot rates. In order to quantify the impacts, a simulation platform is developed based on IxEV-DO technology. | en_US |
| dc.identifier.journal | 8TH WORLD MULTI-CONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XIII, PROCEEDINGS: INDUSTRIAL SYSTEMS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/150680 | |
| dc.identifier.wosnumber | WOS:000227691200053 | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | wireless | en_US |
| dc.subject | CDMA | en_US |
| dc.subject | data | en_US |
| dc.subject | 1xEV-DO | en_US |
| dc.subject | 3G | en_US |
| dc.subject | fairness | en_US |
| dc.subject | scheduler | en_US |
| dc.subject | data model | en_US |
| dc.subject | system throughput | en_US |
| dc.title | Scheduler design issues for wireless high-speed data systems | en_US |
| dc.type | Proceedings Paper | en_US |
Files
License bundle
1 - 1 of 1
Loading...
- Name:
- license.txt
- Size:
- 1.71 KB
- Format:
- Item-specific license agreed to upon submission
- Description: