New serial architecture for the Berlekamp-Massey algorithm
| dc.citation.epage | 483 | en_US |
| dc.citation.issue | 4 | en_US |
| dc.citation.spage | 481 | en_US |
| dc.citation.volume | 47 | en_US |
| dc.contributor.author | Chang, HC | en_US |
| dc.contributor.author | Shung, CB | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:46:43Z | |
| dc.date.available | 2014-12-08T15:46:43Z | |
| dc.date.issued | 1999-04-01 | en_US |
| dc.description.abstract | We propose a new efficient serial architecture to implement the Berlekamp-Massey algorithm, which is frequently used in BCH and Reed-Solomon decoders, An inversionless Berlekamp-Massey algorithm is adopted which not only eliminates the finite-field inverter but also introduces additional parallelism, We discover a clever scheduling of three finite-field multipliers to implement the algorithm very efficiently, Compared to a previously proposed serial Berlekamp-Massey architecture, our technique significantly reduces the latency. | en_US |
| dc.identifier.doi | 10.1109/26.764911 | en_US |
| dc.identifier.issn | 0090-6778 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON COMMUNICATIONS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/26.764911 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/31410 | |
| dc.identifier.wosnumber | WOS:000080420900001 | |
| dc.language.iso | en_US | en_US |
| dc.subject | Bose-Chaudhuri-Hacquenghem (BCH) | en_US |
| dc.title | New serial architecture for the Berlekamp-Massey algorithm | en_US |
| dc.type | Article; Proceedings Paper | en_US |