全數位鎖相迴路設計與應用之研究(II)
| dc.contributor.author | 李鎮宜 | en_US |
| dc.contributor.author | LEE CHEN-YI | en_US |
| dc.contributor.department | 國立交通大學電子工程學系 | zh_TW |
| dc.date.accessioned | 2014-12-13T10:51:01Z | |
| dc.date.available | 2014-12-13T10:51:01Z | |
| dc.date.issued | 2000 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.identifier.govdoc | NSC89-2218-E009-072 | zh_TW |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=597353&docId=112567 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/102459 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | 全數位鎖相迴路設計與應用之研究(II) | zh_TW |
| dc.title | The Study of all Digital Phase Lock Loop Design and Its Applications(II) | en_US |
| dc.type | Plan | en_US |
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