A double-issue java processor design for embedded applications
| dc.citation.epage | 3505 | en_US |
| dc.citation.spage | 3502 | en_US |
| dc.contributor.author | Ko, Hou-Jen | en_US |
| dc.contributor.author | Tsai, Chun-Jen | en_US |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.date.accessioned | 2014-12-08T15:09:35Z | |
| dc.date.available | 2014-12-08T15:09:35Z | |
| dc.date.issued | 2007 | en_US |
| dc.description.abstract | Java applications for embedded systems are becoming popular today. CLDC/MIDP is the standard application platform for mobile phones while CDC/PBP is the emerging application platform for next generation digital TV set-top boxes. Although software-based Java Virtual Machines (VM) are prevalent, most of these VMs require a host processor running at much higher clock rate than 300MHz to reach reasonable performance. This is beyond the recommended specification of handsets and set-top boxes. In this paper, we have proposed a double-issue java processor for embedded systems. The design is not tied to any host processors and can be used as an efficient binary execution engine for a full Java Runtime Environment implementation. When synthesized on a Virtex IV FPGA (4VFX12FF66-10), the RTL model can reach over 100MHz and consumes less than 22% resources of the device. | en_US |
| dc.identifier.doi | 10.1109/ISCAS.2007.378382 | en_US |
| dc.identifier.isbn | 978-1-4244-0920-4 | en_US |
| dc.identifier.issn | 0271-4302 | en_US |
| dc.identifier.journal | 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/ISCAS.2007.378382 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/7323 | |
| dc.identifier.wosnumber | WOS:000251608404145 | |
| dc.language.iso | en_US | en_US |
| dc.title | A double-issue java processor design for embedded applications | en_US |
| dc.type | Article | en_US |