A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications

Abstract

This paper presents the design of a low power programmable PRBS generator and a low noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is capable of producing 2(7)-1, 2(10)-1, 2(15)-1, 2(23)-1, and 2(31)-1 b test pattern according to ITU-T recommendations. High speed and low power operations of the PRBS generator are achieved by 16 paths parallel feedback techniques. The measured jitter of the CMU is only 3.56 ps(rms), and the data jitter at the PRBS output is mainly determined by the CMU. Implemented in a 0.18 mu m CMOS process, the power dissipation for PRBS generator is only 10.8 mW, and the CMU consumes about 87mW.