A new dynamic scaling FFT processor

dc.citation.epage	452	en_US
dc.citation.spage	449	en_US
dc.contributor.author	Lin, YW	en_US
dc.contributor.author	Lee, CY	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:25:52Z
dc.date.available	2014-12-08T15:25:52Z
dc.date.issued	2004	en_US
dc.description.abstract	A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and prefetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 mu m CMOS process with core area of 4.84mm(2) and consumes only 25.2 mW at 20 MHz.	en_US
dc.identifier.isbn	0-7803-8660-4	en_US
dc.identifier.journal	PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18311
dc.identifier.wosnumber	WOS:000227668700113
dc.language.iso	en_US	en_US
dc.title	A new dynamic scaling FFT processor	en_US
dc.type	Proceedings Paper	en_US

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