ESD protection design for mixed-voltage I/O interfaces - Overview

dc.citation.epage	498	en_US
dc.citation.spage	493	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Lin, Kun-Hsien	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:25:20Z
dc.date.available	2014-12-08T15:25:20Z
dc.date.issued	2005	en_US
dc.description.abstract	Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification, and analysis of ESD protection designs for mixed-voltage I/O interfaces are presented and discussed.	en_US
dc.identifier.isbn	978-0-7803-9339-4	en_US
dc.identifier.journal	2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/17723
dc.identifier.wosnumber	WOS:000245210600107
dc.language.iso	en_US	en_US
dc.title	ESD protection design for mixed-voltage I/O interfaces - Overview	en_US
dc.type	Proceedings Paper	en_US

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