SERL: Soft Error Resilient Latch Design
| dc.citation.woscount | 0 | en_US |
| dc.contributor.author | Chang, Chun-Wei (Jacky) | en_US |
| dc.contributor.author | Huang, Hsuan-Ming (Ryan) | en_US |
| dc.contributor.author | Lin, Yuwen | en_US |
| dc.contributor.author | Wen, Charles H. -P. | en_US |
| dc.contributor.department | 電機工程學系 | zh_TW |
| dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2017-04-21T06:49:05Z | |
| dc.date.available | 2017-04-21T06:49:05Z | |
| dc.date.issued | 2016 | en_US |
| dc.description.abstract | Soft errors, radiation-induced transient faults latched by memory elements, have emerged to be one dominant failure mechanism for scaled CMOS designs. Therefore, this paper presents a robust design named soft error resilient latch (SERL). Compared to BISER, one of the latest latch designs, SERL demonstrates better soft error protection with smaller area overhead. | en_US |
| dc.identifier.isbn | 978-1-4673-9498-7 | en_US |
| dc.identifier.journal | 2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/136380 | |
| dc.identifier.wosnumber | WOS:000389516800035 | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | SER | en_US |
| dc.subject | BISER | en_US |
| dc.subject | SEU | en_US |
| dc.subject | SET | en_US |
| dc.title | SERL: Soft Error Resilient Latch Design | en_US |
| dc.type | Proceedings Paper | en_US |
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