Oscillation ring based interconnect test scheme for SOC

dc.citation.epage	187	en_US
dc.citation.spage	184	en_US
dc.contributor.author	Li, Katherine Shu-Min	en_US
dc.contributor.author	Lee, Chung Len	en_US
dc.contributor.author	Su, Chauchin	en_US
dc.contributor.author	Chen, Jwu E.	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:25:28Z
dc.date.available	2014-12-08T15:25:28Z
dc.date.issued	2005	en_US
dc.description.abstract	We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.	en_US
dc.identifier.isbn	0-7803-8736-8	en_US
dc.identifier.journal	ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/17866
dc.identifier.wosnumber	WOS:000245021700039
dc.language.iso	en_US	en_US
dc.title	Oscillation ring based interconnect test scheme for SOC	en_US
dc.type	Proceedings Paper	en_US

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