ADDRESS GENERATION APPARATUS AND METHOD FOR QUADRATIC PERMUTATION POLYNOMIAL INTERLEAVER
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 20120047414 | zh_TW |
| dc.contributor.author | LEE SHUENN-GI | en_US |
| dc.contributor.author | WANG CHUNG HSUAN | en_US |
| dc.contributor.author | SHEEN WERN-HO | en_US |
| dc.date.accessioned | 2014-12-16T06:15:17Z | |
| dc.date.available | 2014-12-16T06:15:17Z | |
| dc.date.issued | 2012-02-23 | en_US |
| dc.description.abstract | An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function Π(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0≦i≦k−1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where Π(i) is also a ith interleaving address generated by the apparatus. | zh_TW |
| dc.identifier.govdoc | H03M013/05 | zh_TW |
| dc.identifier.govdoc | G06F011/08 | zh_TW |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/105210 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | ADDRESS GENERATION APPARATUS AND METHOD FOR QUADRATIC PERMUTATION POLYNOMIAL INTERLEAVER | zh_TW |
| dc.type | Patents | en_US |