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The IC design of a high speed RSA processor

dc.citation.epage36en_US
dc.citation.spage33en_US
dc.contributor.authorYang, CCen_US
dc.contributor.authorJen, CWen_US
dc.contributor.authorChang, TSen_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:27:38Z
dc.date.available2014-12-08T15:27:38Z
dc.date.issued1996en_US
dc.description.abstractIn this paper, we proposed a new algorithm based on Montgomery's algorithm[1] to calculate modular multiplication that is the core arithmetic operation in RSA cryptosystem. Since the critical path delay in modular multiplication operation is reduced the new design yields a very fast implementation. We have implemented a 512-bit single chip RSA processor based on our modified algorithm with Compass 0.6 mu n SPDM cell library. By our modified modular exponentiation algorithm if takes about 1.5n(2) clock cycles to finish one n-bit RSA modular exponentiation operation in our architecture. The simulation results show that we can operate up to 125Mhz, therefore the baud rate of our 512-bit RSA processor is about 164k bits/sec.en_US
dc.identifier.isbn0-7803-3702-6en_US
dc.identifier.journalAPCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/19887
dc.identifier.wosnumberWOS:A1996BH25U00010
dc.language.isoen_USen_US
dc.titleThe IC design of a high speed RSA processoren_US
dc.typeProceedings Paperen_US

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