系統晶片後端設計變更之繞線研究
| dc.contributor.author | 李毅郎 | en_US |
| dc.contributor.author | Li Yih-Lang | en_US |
| dc.contributor.department | 國立交通大學資訊科學學系 | zh_TW |
| dc.date.accessioned | 2014-12-13T10:32:54Z | |
| dc.date.available | 2014-12-13T10:32:54Z | |
| dc.date.issued | 2003 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.identifier.govdoc | NSC92-2218-E009-013 | zh_TW |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=874724&docId=167676 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/91782 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | 系統晶片後端設計變更之繞線研究 | zh_TW |
| dc.title | An Efficient ECO Router for SoC Designs | en_US |
| dc.type | Plan | en_US |