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Memory-based FFT/IFFT processor and design method for general sized memory-based FFT processor

dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber08364736zh_TW
dc.contributor.authorLee Chen-Yien_US
dc.contributor.authorHsiao Chen-Fongen_US
dc.contributor.authorChen Yuanen_US
dc.date.accessioned2014-12-16T06:14:06Z
dc.date.available2014-12-16T06:14:06Z
dc.date.issued2013-01-29en_US
dc.description.abstractFor a large size FFT computation, this invention decomposes it into several smaller sizes FFT by decomposition equation and then transform the original index from one dimension into multi-dimension vector. By controlling the index vector, this invention could distribute the input data into different memory banks such that both the in-place policy for computation and the multi-bank memory for high-radix structure could be supported simultaneously without memory conflict. Besides, in order to keep memory conflict-free when the in-place policy is also adopted for I/O data, this invention reverses the decompose order of FFT to satisfy the vector reverse behavior. This invention can minimize the area and reduce the necessary clock rate effectively for general sized memory-based FFT processor design.zh_TW
dc.identifier.govdocG06F017/14zh_TW
dc.identifier.govdocG06F015/00zh_TW
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/104515
dc.language.isozh_TWen_US
dc.titleMemory-based FFT/IFFT processor and design method for general sized memory-based FFT processorzh_TW
dc.typePatentsen_US

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