Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices
| dc.citation.epage | 30 | en_US |
| dc.citation.spage | 27 | en_US |
| dc.contributor.author | Yang, Hao-I | en_US |
| dc.contributor.author | Chuang, Ching-Te | en_US |
| dc.contributor.author | Hwang, Wei | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:25:24Z | |
| dc.date.available | 2014-12-08T15:25:24Z | |
| dc.date.issued | 2009 | en_US |
| dc.description.abstract | The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, V(T). drifts Caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of natroscale SPAM with high-kappa, metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated. | en_US |
| dc.identifier.doi | 10.1109/MTDT.2009.25 | en_US |
| dc.identifier.isbn | 978-0-7695-3797-9 | en_US |
| dc.identifier.journal | 2009 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING, PROCEEDINGS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/MTDT.2009.25 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/17803 | |
| dc.identifier.wosnumber | WOS:000275814000005 | |
| dc.language.iso | en_US | en_US |
| dc.title | Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices | en_US |
| dc.type | Proceedings Paper | en_US |