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Analysis of the Scaling Effect on NAND Flash Memory Cell Operation

dc.citation.epage35en_US
dc.citation.issue34en_US
dc.citation.spage27en_US
dc.citation.volume50en_US
dc.contributor.authorShirota, R.en_US
dc.contributor.authorWatanabe, H.en_US
dc.contributor.department電機資訊學士班zh_TW
dc.contributor.departmentUndergraduate Honors Program of Electrical Engineering and Computer Scienceen_US
dc.date.accessioned2014-12-08T15:36:13Z
dc.date.available2014-12-08T15:36:13Z
dc.date.issued2013en_US
dc.description.abstractIn recent years, the enormous success of NAND Flash memory technology in realizing multi-gigabyte memory chips has evidently triggered a lot of difficulties concerning its cell operation, such as parasitic neighbouring cell coupling, FN-tunnelling statistics, Vt distribution widening by RTN, et al. In this paper, two kinds of phenomena are shown. One is the increase of the interface state density after write/erase cycles, which will degrades the subthreshold swing (SS) of the memory cell in the NAND string. The other is the increase of the programmed Vt distribution after programming, which also reduces the cell operation margin. It is revealed that Vt distribution widening closely depends on the floating gate doping concentration of Phosphorus. These phenomena become more serious as cell size smaller.en_US
dc.identifier.doi10.1149/05034.0027ecsten_US
dc.identifier.isbn978-1-60768-422-0en_US
dc.identifier.issn1938-5862en_US
dc.identifier.journalNONVOLATILE MEMORIESen_US
dc.identifier.urihttp://dx.doi.org/10.1149/05034.0027ecsten_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/24557
dc.identifier.wosnumberWOS:000338081400004
dc.language.isoen_USen_US
dc.titleAnalysis of the Scaling Effect on NAND Flash Memory Cell Operationen_US
dc.typeProceedings Paperen_US

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