An integrated 60-GHz front-end receiver with a frequency tripler using 0.13-mu m CMOS technology
| dc.citation.epage | 832 | en_US |
| dc.citation.spage | 829 | en_US |
| dc.contributor.author | Chen, Po-Hung | en_US |
| dc.contributor.author | Chen, Min-Chiao | en_US |
| dc.contributor.author | Wu, Chung-Yu | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:13:17Z | |
| dc.date.available | 2014-12-08T15:13:17Z | |
| dc.date.issued | 2007 | en_US |
| dc.description.abstract | In this paper, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is proposed. The proposed receiver consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler. This chip is designed using 0.13-mu m CMOS technology. By using a frequency tripler, the operating frequency of the PLL can be reduced from 60 GHz to 20 GHz. This makes the implementation of the PLL much easier. According to the simulation results, the receiver has a noise figure (NF) of 7.6 dB, a power gain of 29.2 dB. It consumes 14.2 mW from a 1.2-V power supply. | en_US |
| dc.identifier.doi | 10.1109/ICECS.2007.4511119 | en_US |
| dc.identifier.isbn | 978-1-4244-1377-5 | en_US |
| dc.identifier.journal | 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/ICECS.2007.4511119 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/10267 | |
| dc.identifier.wosnumber | WOS:000255014801028 | |
| dc.language.iso | en_US | en_US |
| dc.title | An integrated 60-GHz front-end receiver with a frequency tripler using 0.13-mu m CMOS technology | en_US |
| dc.type | Proceedings Paper | en_US |