最少無靜態障礙組合邏輯線路之計算機傾向合成法

Abstract

Hazard phenomenon is one of the most improtant problem in digital system design. It is due to unequal delay time of each gate in combinational logic Ckt. For any given switching function of within 4 variables, we can detect and eliminate it from Karnaugh map easily [7,8]. If the number of variables of given switching function is more than four, then this method is tedius and time consuming. It will be shown that by using modified extraction algorithm, we can obtain minimum static hazard-free combinational logic conveniently.