A low-voltage low-distortion MOS sampling switch

dc.citation.epage	3134	en_US
dc.citation.spage	3131	en_US
dc.contributor.author	Yang, CY	en_US
dc.contributor.author	Hung, CC	en_US
dc.contributor.department	電信工程研究所	zh_TW
dc.contributor.department	Institute of Communications Engineering	en_US
dc.date.accessioned	2014-12-08T15:25:23Z
dc.date.available	2014-12-08T15:25:23Z
dc.date.issued	2005	en_US
dc.description.abstract	In order to reduce distortion due to variation of the gate overdrive and the threshold voltage, a novel low-voltage constant-resistance sampling switch is proposed in this paper. The technique to reduce nonlinearity can be used in a high resolution sample and hold circuit. TSMC 0.18um standard CMOS technology is utilized in this research. Results indicate that much lower Total Harmonic Distortion (THD) is achieved by the proposed circuit. The low THD meets the requirements in the application of the low-voltage low-distortion switched-capacitor circuits.	en_US
dc.identifier.isbn	0-7803-8834-8	en_US
dc.identifier.issn	0271-4302	en_US
dc.identifier.journal	2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/17775
dc.identifier.wosnumber	WOS:000232002403029
dc.language.iso	en_US	en_US
dc.title	A low-voltage low-distortion MOS sampling switch	en_US
dc.type	Proceedings Paper	en_US

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