A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMS

dc.citation.epage	50	en_US
dc.citation.spage	47	en_US
dc.contributor.author	Wu, CY	en_US
dc.contributor.author	Yu-Yee, L	en_US
dc.contributor.department	電子物理學系	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electrophysics	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:27:12Z
dc.date.available	2014-12-08T15:27:12Z
dc.date.issued	1999	en_US
dc.description.abstract	A novel 1.5-bit (3-level)/cell storage technique is described. This sense amplifier of DRAM can sense the ternary state. Thus, this structure can effectively reduce the bit-cost. The proposed DRAM can be operated at 1.5V without changing the common DRAM process.	en_US
dc.identifier.isbn	0-7803-5471-0	en_US
dc.identifier.journal	ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/19416
dc.identifier.wosnumber	WOS:000081715100012
dc.language.iso	en_US	en_US
dc.title	A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMS	en_US
dc.type	Proceedings Paper	en_US

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