The Impact of Fin/Sidewall/Gate Line Edge Roughness on Trapezoidal Bulk FinFET Devices

Abstract

In this work, the DC characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFET induced by different line edge roughness (LER) is for the first time studied by using experimentally validated 3D device simulation. By considering a time-domain Gaussian noise function, we compare four types of LER: Fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFET with respect to different fin angles. The resist-LER and sidewall-LER have large impact on characteristics fluctuation. For each type of LER, the Vth fluctuation is comparable among fin angles.