Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology

Abstract

On-chip : electrostatic discharge (ESD) protection circuits had been built in IC chips to protect the devices and circuits against ESD damage. But, ESD protection circuits constructed with the scaled-down CMOS devices are very weak to ESD stress. Therefore, novel ESD protection solutions must be developed to overcome this reliability challenge for integrated circuits fabricated in the nano-scale CMOS technology. In this paper, the whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology has been proposed with two main methods. One is the substrate-triggered circuit technique used to effectively improve ESD robustness of devices in the nano-scale CMOS technology. The other is the novel design concept of "ESD Buses" used to solve the internal ESD damage issue of CMOS IC with multiple and separated power lines. The internal circuits or interface circuits, realized by nano-scale CMOS devices, are more sensitive to such internal ESD damage issue. By using ESD buses, ESD current can be quickly discharged far away from the internal circuits or interface circuits of CMOS IC to achieve the goal of whole-chip ESD protection.