Memory-hierarchy-based power reduction for H.264/AVC video decoder

dc.citation.epage	250	en_US
dc.citation.spage	247	en_US
dc.contributor.author	Liu, Tsu-Ming	en_US
dc.contributor.author	Lee, Chen-Yi	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:24:57Z
dc.date.available	2014-12-08T15:24:57Z
dc.date.issued	2006	en_US
dc.description.abstract	Memory storage is crucial power factor in H.264/AVC video decoding system. In this paper, we exploit three-level of memory hierarchy to break the data dependency and reduce the number of access for external memory. further, we apply line-pixel-lookahead (LPL) scheme to make a compromise between power consumption and internal memory cost. Experimental results prove that about 50% of memory power reduction can be achieved as compared to comparable decoders without exploiting memory hierarchy [1][2].	en_US
dc.identifier.isbn	1-4244-0179-8	en_US
dc.identifier.journal	2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/17320
dc.identifier.wosnumber	WOS:000239709500064
dc.language.iso	en_US	en_US
dc.title	Memory-hierarchy-based power reduction for H.264/AVC video decoder	en_US
dc.type	Proceedings Paper	en_US

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