E-Home核心技術之研究---子計畫五晶片上匯流排之架構設計及效能分析技術(I)
| dc.contributor.author | 黃俊達 | en_US |
| dc.contributor.author | Huang Juinn-Dar | en_US |
| dc.contributor.department | 交通大學電子工程系 | zh_TW |
| dc.date.accessioned | 2014-12-13T10:31:42Z | |
| dc.date.available | 2014-12-13T10:31:42Z | |
| dc.date.issued | 2004 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.identifier.govdoc | NSC93-2220-E009-029 | zh_TW |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=1030986&docId=196434 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/91118 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | E-Home核心技術之研究---子計畫五晶片上匯流排之架構設計及效能分析技術(I) | zh_TW |
| dc.title | Technologies on Architecture Design and Performance Analysis of On-Chip Bus(I) | en_US |
| dc.type | Plan | en_US |
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