Good 150 degrees C Retention and Fast Erase Characteristics in Charge-Trap-Engineered Memory having a Scaled Si3N4 Layer

Abstract

We report a new charge-trap-engineered flash non-volatile memory that has combined 5nm Si3N4 and 0.9nm EOT HfON trapping layers, within double-barrier and double-tunnel layers. At 150 degrees C under a 100 mu s and +/- 16V P/E, this device showed good device integrity of a 5.6V initial Delta V-th window and 3.8V 10-year extrapolated retention window. These data are better than the 3.3V initial Delta V-th and 1.7V 10-year data for a similar structure not having the extra WON layer.