ESD Protection Design for High-Speed Applications in CMOS Technology

dc.citation.epage	308	en_US
dc.citation.spage	305	en_US
dc.contributor.author	Chen, Jie-Ting	en_US
dc.contributor.author	Lin, Chun-Yu	en_US
dc.contributor.author	Chang, Rong-Kun	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Tzeng, Tzu-Chien	en_US
dc.contributor.author	Lin, Tzu-Chiang	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2018-08-21T05:56:49Z
dc.date.available	2018-08-21T05:56:49Z
dc.date.issued	2016-01-01	en_US
dc.description.abstract	To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded silicon-controlled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.	en_US
dc.identifier.issn	1548-3746	en_US
dc.identifier.journal	2016 IEEE 59TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/146687
dc.identifier.wosnumber	WOS:000404343800077	en_US
dc.language.iso	en_US	en_US
dc.title	ESD Protection Design for High-Speed Applications in CMOS Technology	en_US
dc.type	Proceedings Paper	en_US

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