An hardware efficient deblocking filter for H.264/AVC

Abstract

This paper presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with only gate count of 9.16K when synthesized from verilog RTL design by using UMC 0.18 mu m CMOS technology. When clocked at 82.58MHz, our design can easily support real-time deblocking of 2Kx1K@30Hz video application, this high performance can meet high resolution real-time application requirement.