DESIGN OF 2xV(DD) LOGIC GATES WITH ONLY 1xV(DD) DEVICES IN NANOSCALE CMOS TECHNOLOGY
| dc.citation.epage | 36 | en_US |
| dc.citation.spage | 33 | en_US |
| dc.citation.woscount | 0 | en_US |
| dc.contributor.author | Chiu, Po-Yen | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.department | 電機學院 | zh_TW |
| dc.contributor.department | College of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2015-07-21T08:31:00Z | |
| dc.date.available | 2015-07-21T08:31:00Z | |
| dc.date.issued | 2013-01-01 | en_US |
| dc.description.abstract | The novel 2xV(DD) NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1xV(DD) devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2xV(DD) tolerant capability. Thus, the new 2xV(DD) logic gates can be operated under 2xV(DD) voltage environment without suffering the gate-oxide reliability issue. | en_US |
| dc.identifier.isbn | 978-1-4799-1166-0 | en_US |
| dc.identifier.issn | 2164-1676 | en_US |
| dc.identifier.journal | 2013 IEEE 26TH INTERNATIONAL SOC CONFERENCE (SOCC) | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/125063 | |
| dc.identifier.wosnumber | WOS:000351736000001 | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | DESIGN OF 2xV(DD) LOGIC GATES WITH ONLY 1xV(DD) DEVICES IN NANOSCALE CMOS TECHNOLOGY | en_US |
| dc.type | Proceedings Paper | en_US |
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