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A Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with V(dd)/AM and V(dd)/PM Compensations in EER System

dc.citation.epage50en_US
dc.citation.spage47en_US
dc.contributor.authorTsou, Wen-Anen_US
dc.contributor.authorWuen, Wen-Shenen_US
dc.contributor.authorWen, Kuei-Annen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:24:30Z
dc.date.available2014-12-08T15:24:30Z
dc.date.issued2009en_US
dc.description.abstractAn auto-biasing cascode class-E PA which can compensate the V(dd)/AM and V(dd)/PM distortion resulting from supply modulation has been proposed. The output voltage of auto-biasing control circuit is generated and varied linearly with PA's supply voltage so that the cascode transistor is degenerated into a resistance and the PA's nonlinear distortion can be compensated. The simulation result shows that the distortion is compensated evidently and the system co-simulation demonstrated that system EVM can be improved from -17 to -19dB. Also, the drain efficiency of the PA can be improved 15% within small supply voltage range.en_US
dc.identifier.doi10.1109/PACCS.2009.109en_US
dc.identifier.isbn978-0-7695-3614-9en_US
dc.identifier.journalPROCEEDINGS OF THE 2009 PACIFIC-ASIA CONFERENCE ON CIRCUITS, COMMUNICATIONS AND SYSTEMen_US
dc.identifier.urihttp://dx.doi.org/10.1109/PACCS.2009.109en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/16999
dc.identifier.wosnumberWOS:000273677100012
dc.language.isoen_USen_US
dc.subjectTrnsmittersen_US
dc.subjectclass-E power amplifieren_US
dc.subjectenvelope elimination and restoration (EER)en_US
dc.titleA Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with V(dd)/AM and V(dd)/PM Compensations in EER Systemen_US
dc.typeProceedings Paperen_US

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