System-level ESD protection design with on-chip transient detection circuit
| dc.citation.epage | 619 | en_US |
| dc.citation.spage | 616 | en_US |
| dc.contributor.author | Yen, Cheng-Cheng | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.author | Shih, Pi-Chia | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:25:03Z | |
| dc.date.available | 2014-12-08T15:25:03Z | |
| dc.date.issued | 2006 | en_US |
| dc.description.abstract | A new on-chip transient detection circuit for system-level electrostatic (d) under bar ischarge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit has been analyzed to fix the system-level ESD issues. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-mu m CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. | en_US |
| dc.identifier.doi | 10.1109/ICECS.2006.379864 | en_US |
| dc.identifier.isbn | 978-1-4244-0394-3 | en_US |
| dc.identifier.journal | 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/ICECS.2006.379864 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/17421 | |
| dc.identifier.wosnumber | WOS:000252489600154 | |
| dc.language.iso | en_US | en_US |
| dc.title | System-level ESD protection design with on-chip transient detection circuit | en_US |
| dc.type | Proceedings Paper | en_US |