針對晶片系統連接網路之驗證與自動合成之研究(III)
| dc.contributor.author | 周景揚 | en_US |
| dc.contributor.author | JOU JING-YANG | en_US |
| dc.contributor.department | 交通大學電子工程系 | zh_TW |
| dc.date.accessioned | 2014-12-13T10:32:06Z | |
| dc.date.available | 2014-12-13T10:32:06Z | |
| dc.date.issued | 2004 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.identifier.govdoc | NSC93-2215-E009-011 | zh_TW |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=1026636&docId=195162 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/91373 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | 針對晶片系統連接網路之驗證與自動合成之研究(III) | zh_TW |
| dc.title | The Study on Interconnection Verification and Synthesis for SoC(III) | en_US |
| dc.type | Plan | en_US |