Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
| dc.citation.epage | 116 | en_US |
| dc.citation.spage | 113 | en_US |
| dc.contributor.author | Ker, MD | en_US |
| dc.contributor.author | Jiang, HC | en_US |
| dc.contributor.author | Peng, JJ | en_US |
| dc.contributor.author | Shieh, TL | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:26:50Z | |
| dc.date.available | 2014-12-08T15:26:50Z | |
| dc.date.issued | 2001 | en_US |
| dc.description.abstract | A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately. | en_US |
| dc.identifier.isbn | 0-7803-7057-0 | en_US |
| dc.identifier.journal | ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/19091 | |
| dc.identifier.wosnumber | WOS:000176019100028 | |
| dc.language.iso | en_US | en_US |
| dc.title | Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's | en_US |
| dc.type | Proceedings Paper | en_US |
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