A low-voltage CMOS LNA design utilizing the technique of capacitive feedback matching network
| dc.citation.epage | 81 | en_US |
| dc.citation.spage | 78 | en_US |
| dc.contributor.author | Wu, Chung-Yu | en_US |
| dc.contributor.author | Shahroury, Fadi Riad | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:25:03Z | |
| dc.date.available | 2014-12-08T15:25:03Z | |
| dc.date.issued | 2006 | en_US |
| dc.description.abstract | In this paper, a CMOS low noise amplifier (LNA) with a new input matching topology has been proposed, analyzed, and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18-mu m 1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NFmin of 4.46 dB. The reverse isolation S12 of the LNA can achieve -40 dB and the input and output return losses are better than -11 dB. The input 1-dB compression point is -11 dBm. This LNA drains 10 mA from the supply voltage of 1 V. | en_US |
| dc.identifier.doi | 10.1109/ICECS.2006.379705 | en_US |
| dc.identifier.isbn | 978-1-4244-0394-3 | en_US |
| dc.identifier.journal | 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/ICECS.2006.379705 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/17418 | |
| dc.identifier.wosnumber | WOS:000252489600020 | |
| dc.language.iso | en_US | en_US |
| dc.title | A low-voltage CMOS LNA design utilizing the technique of capacitive feedback matching network | en_US |
| dc.type | Proceedings Paper | en_US |