高密度多層構裝基板與接合材料研究---子計畫II：銅接合-低介電材料介電層之界面可靠度提昇研究(III)

dc.contributor.author	邱碧秀	en_US
dc.contributor.author	CHIOU BI-SHIOU	en_US
dc.contributor.department	國立交通大學電子工程學系	zh_TW
dc.date.accessioned	2014-12-13T10:36:18Z
dc.date.available	2014-12-13T10:36:18Z
dc.date.issued	2001	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.identifier.govdoc	NSC90-2216-E009-032	zh_TW
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=673263&docId=128265	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/93855
dc.language.iso	zh_TW	en_US
dc.subject	多層基板	zh_TW
dc.subject	低介電材料	zh_TW
dc.subject	界面可靠度	zh_TW
dc.subject	高密度	zh_TW
dc.subject	銅互接	zh_TW
dc.subject	Multilayer substrate	en_US
dc.subject	Low dielectric material	en_US
dc.subject	Interfacial reliability	en_US
dc.subject	High density	en_US
dc.subject	Copper interconnection	en_US
dc.title	高密度多層構裝基板與接合材料研究---子計畫II：銅接合-低介電材料介電層之界面可靠度提昇研究(III)	zh_TW
dc.title	Reliability Enhancement for Copper Interconnect-Low K Dielectric Interface (III)	en_US
dc.type	Plan	en_US

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