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NONVOLATILE MEMORY AND ITS OPERATION METHOD THEREOF

dc.citation.patentcountryUSAen_US
dc.citation.patentnumber20180294406en_US
dc.contributor.authorSteve S. CHUNGen_US
dc.contributor.authorE-Ray HSIEHen_US
dc.date.accessioned2019-04-11T06:08:29Z
dc.date.available2019-04-11T06:08:29Z
dc.date.issued2018-10-11en_US
dc.description.abstractA first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.en_US
dc.identifier.govdocH01L045/00en_US
dc.identifier.govdocH01L027/24en_US
dc.identifier.govdocG11C013/00en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/151442
dc.language.isoen_USen_US
dc.titleNONVOLATILE MEMORY AND ITS OPERATION METHOD THEREOFen_US
dc.typePatentsen_US

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