高介電閘氧化層深次微米MOS元件電漿製程傷害可靠性之研究

dc.contributor.author	莊紹勳	en_US
dc.contributor.author	Chung Steve S	en_US
dc.contributor.department	國立交通大學電子工程學系	zh_TW
dc.date.accessioned	2014-12-13T10:39:32Z
dc.date.available	2014-12-13T10:39:32Z
dc.date.issued	2001	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.identifier.govdoc	NSC90-2215-E009-065	zh_TW
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=665692&docId=126371	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/96596
dc.language.iso	zh_TW	en_US
dc.subject	高介電閘	zh_TW
dc.subject	介電層	zh_TW
dc.subject	電漿製程	zh_TW
dc.subject	可靠性	zh_TW
dc.subject	金氧半場效電晶體	zh_TW
dc.subject	High dielectric gate	en_US
dc.subject	Dielectric layer	en_US
dc.subject	Plasma process	en_US
dc.subject	Reliability	en_US
dc.subject	MOSFET	en_US
dc.title	高介電閘氧化層深次微米MOS元件電漿製程傷害可靠性之研究	zh_TW
dc.title	Study of the Plasma Induced Reliabilities in High-K Gate Dielectric Submicron MOSFETs	en_US
dc.type	Plan	en_US

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