針對3D整合之電子設計自動化技術開發---子計畫三：針對三維規則型邏輯結構之架構探索及穩健合成系統開發(II)
| dc.contributor.author | 黃俊達 | en_US |
| dc.contributor.author | Huang Juinn-Dar | en_US |
| dc.contributor.department | 國立交通大學電子工程學系及電子研究所 | zh_TW |
| dc.date.accessioned | 2014-12-13T10:45:02Z | |
| dc.date.available | 2014-12-13T10:45:02Z | |
| dc.date.issued | 2010 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.identifier.govdoc | NSC99-2220-E009-037 | zh_TW |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=2158310&docId=347321 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/100252 | |
| dc.language.iso | zh_TW | en_US |
| dc.subject | 規則型邏輯結構 | zh_TW |
| dc.subject | 架構探索 | zh_TW |
| dc.subject | 產能最佳化 | zh_TW |
| dc.subject | 多時脈溝通 | zh_TW |
| dc.subject | 高階合成 | zh_TW |
| dc.subject | 設計方法論 | zh_TW |
| dc.subject | 設計自動化 | zh_TW |
| dc.subject | Regular logic architecture | en_US |
| dc.subject | architecture exploration | en_US |
| dc.subject | throughput optimization | en_US |
| dc.subject | multicycle communication | en_US |
| dc.subject | high-level synthesis | en_US |
| dc.subject | design methodology | en_US |
| dc.subject | and design automation. | en_US |
| dc.title | 針對3D整合之電子設計自動化技術開發---子計畫三：針對三維規則型邏輯結構之架構探索及穩健合成系統開發(II) | zh_TW |
| dc.title | Architecture Exploration and Robust Synthesis Framework Development for 3D Regular Logic Structure (II) | en_US |
| dc.type | Plan | en_US |