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Novel Silicon Surface Pre-Treatment (SSPT) technique for CMOS device performance boosting

dc.citation.spage42en_US
dc.citation.woscount0en_US
dc.contributor.authorLee, Da-Yuanen_US
dc.contributor.authorChen, C. C.en_US
dc.contributor.authorHuang, C. H.en_US
dc.contributor.authorLim, P. S.en_US
dc.contributor.authorChan, M. H.en_US
dc.contributor.authorYeh, M. S.en_US
dc.contributor.authorHuang, C. S.en_US
dc.contributor.authorTao, H. J.en_US
dc.contributor.authorMii, Y. J.en_US
dc.contributor.department光電工程學系zh_TW
dc.contributor.departmentDepartment of Photonicsen_US
dc.date.accessioned2019-04-02T06:04:43Z
dc.date.available2019-04-02T06:04:43Z
dc.date.issued2008-01-01en_US
dc.description.abstractIn this paper, a novel surface treatment technique using Silicon Surface Pre-Treatment (SSPT) technique to boost high performance CMOS circuit is reported. This approach provides a smooth silicon surface and extends the effective channel width to enhance device performance on both N and PMOSFET. In this work, a smooth and rounded active area (AA) surface was successfully fabricated. Using this technique, we demonstrated a significant device boost of 15% and 7% on small dimension N and PMOSFET, respectively. These achievements were demonstrated without negative impact on GOI and NBTI.en_US
dc.identifier.doi10.1109/VTSA.2008.4530790en_US
dc.identifier.journal2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAMen_US
dc.identifier.urihttp://dx.doi.org/10.1109/VTSA.2008.4530790en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/151150
dc.identifier.wosnumberWOS:000256564900019en_US
dc.language.isoen_USen_US
dc.titleNovel Silicon Surface Pre-Treatment (SSPT) technique for CMOS device performance boostingen_US
dc.typeProceedings Paperen_US

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