0.1 mu m poly-Si thin film transistors for system-on-panel (SoP) applications
| dc.citation.epage | 936 | en_US |
| dc.citation.spage | 933 | en_US |
| dc.contributor.author | Tsui, BY | en_US |
| dc.contributor.author | Lin, CP | en_US |
| dc.contributor.author | Huang, CF | en_US |
| dc.contributor.author | Xiao, YH | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:25:11Z | |
| dc.date.available | 2014-12-08T15:25:11Z | |
| dc.date.issued | 2005 | en_US |
| dc.description.abstract | Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 mu m channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated. | en_US |
| dc.identifier.isbn | 0-7803-9268-X | en_US |
| dc.identifier.journal | IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/17583 | |
| dc.identifier.wosnumber | WOS:000236225100213 | |
| dc.language.iso | en_US | en_US |
| dc.title | 0.1 mu m poly-Si thin film transistors for system-on-panel (SoP) applications | en_US |
| dc.type | Proceedings Paper | en_US |
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