A BENDING N-WELL BALLAST LAYOUT TO IMPROVE ESD ROBUSTNESS IN FULLY-SILICIDED CMOS TECHNOLOGY
| dc.citation.epage | 860 | en_US |
| dc.citation.spage | 857 | en_US |
| dc.contributor.author | Wen, Yong-Ru | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.author | Chen, Wen-Yi | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:39:26Z | |
| dc.date.available | 2014-12-08T15:39:26Z | |
| dc.date.issued | 2010 | en_US |
| dc.description.abstract | Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS. | en_US |
| dc.identifier.doi | 10.1109/IRPS.2010.5488718 | en_US |
| dc.identifier.isbn | 978-1-4244-5431-0 | en_US |
| dc.identifier.journal | 2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/IRPS.2010.5488718 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/26931 | |
| dc.identifier.wosnumber | WOS:000287515600142 | |
| dc.language.iso | en_US | en_US |
| dc.title | A BENDING N-WELL BALLAST LAYOUT TO IMPROVE ESD ROBUSTNESS IN FULLY-SILICIDED CMOS TECHNOLOGY | en_US |
| dc.type | Article | en_US |