SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
| dc.citation.patentcountry | USA | en_US |
| dc.citation.patentnumber | 20180175185 | en_US |
| dc.contributor.author | Edward Yi CHANG | en_US |
| dc.contributor.author | Shih-Chien LIU | en_US |
| dc.contributor.author | Chung-Kai HUANG | en_US |
| dc.contributor.author | Chia-Hsun WU | en_US |
| dc.contributor.author | Ping-Cheng HAN | en_US |
| dc.contributor.author | Yueh-Chin LIN | en_US |
| dc.contributor.author | Ting-En HSIEH | en_US |
| dc.date.accessioned | 2019-04-11T06:08:08Z | |
| dc.date.available | 2019-04-11T06:08:08Z | |
| dc.date.issued | 2018-06-21 | en_US |
| dc.description.abstract | A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The barrier layer has a recess, and a portion of the barrier layer under the recess has a thickness. The source and the drain are disposed on the barrier layer. The charge trapping layer covers the bottom of the recess. The ferroelectric material is disposed on the charge trapping layer. The gate is disposed on the ferroelectric material. | en_US |
| dc.identifier.govdoc | H01L029/778 | en_US |
| dc.identifier.govdoc | H01L029/51 | en_US |
| dc.identifier.govdoc | H01L021/28 | en_US |
| dc.identifier.govdoc | H01L029/40 | en_US |
| dc.identifier.govdoc | H01L029/423 | en_US |
| dc.identifier.govdoc | H01L029/66 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/151430 | |
| dc.language.iso | en_US | en_US |
| dc.title | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | en_US |
| dc.type | Patents | en_US |