ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN
| dc.citation.epage | D174 | en_US |
| dc.citation.spage | D171 | en_US |
| dc.contributor.author | SHEN, WZ | en_US |
| dc.contributor.author | TAO, YH | en_US |
| dc.contributor.author | DUNG, LR | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:27:55Z | |
| dc.date.available | 2014-12-08T15:27:55Z | |
| dc.date.issued | 1994 | en_US |
| dc.identifier.isbn | 0-7803-1915-X | en_US |
| dc.identifier.journal | 1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4: VLSI | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/20185 | |
| dc.identifier.wosnumber | WOS:A1994BB77Z00043 | |
| dc.language.iso | en_US | en_US |
| dc.title | ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN | en_US |
| dc.type | Proceedings Paper | en_US |
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