High-throughput pipelined FFT processor

Abstract

The invention proposes a pipelined FFT processor for UWB system, comprising a first module for implementing radix-2 FFT algorithm; a second module is to realize radix-8 FFT algorithm; a third module is to realize radix-8 FFT algorithm; a plurality of conjugate blocks; a division block; and a plurality of multiplexers. The proposed pipelined FFT architecture called Mixed-Radix Multi-Path Delay Feedback (MRMDF) can provide higher throughput rate by using the multi-data-path scheme. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications.