Three-dimensional integrated circuit
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 08890303 | zh_TW |
| dc.contributor.author | Tan An-Nan | en_US |
| dc.contributor.author | Chen Hung-Ming | en_US |
| dc.date.accessioned | 2014-12-16T06:13:47Z | |
| dc.date.available | 2014-12-16T06:13:47Z | |
| dc.date.issued | 2014-11-18 | en_US |
| dc.description.abstract | A three-dimensional integrated circuit, including a first adhesive bonding layer, a first chip, a second chip, and an inter-stratum thermal pad, is provided. The first adhesive bonding layer has a first surface and a second surface opposite to each other. The first chip is disposed on the first surface of the first adhesive bonding layer. The first chip includes a hot zone. The second chip is disposed on the second surface of the first adhesive bonding layer. The inter-stratum thermal pad is embedded in the first adhesive bonding layer and faces to the hot zone. | zh_TW |
| dc.identifier.govdoc | H01L023/36 | zh_TW |
| dc.identifier.govdoc | H01L023/367 | zh_TW |
| dc.identifier.govdoc | H01L023/48 | zh_TW |
| dc.identifier.govdoc | H01L025/065 | zh_TW |
| dc.identifier.govdoc | H01L023/42 | zh_TW |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/104328 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | Three-dimensional integrated circuit | zh_TW |
| dc.type | Patents | en_US |