DYNAMIC RECONFIGURABLE HETEROGENEOUS PROCESSOR ARCHITECTURE WITH LOAD BALANCING AND DYNAMIC ALLOCATION METHOD THEREOF
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 20140157285 | zh_TW |
| dc.contributor.author | CHUNG Chung-Ping | en_US |
| dc.contributor.author | YANG Hui-Chin | en_US |
| dc.contributor.author | CHEN Yi-Chi | en_US |
| dc.date.accessioned | 2014-12-16T06:14:48Z | |
| dc.date.available | 2014-12-16T06:14:48Z | |
| dc.date.issued | 2014-06-05 | en_US |
| dc.description.abstract | A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamic reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost. | zh_TW |
| dc.identifier.govdoc | G06F009/50 | zh_TW |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/104909 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | DYNAMIC RECONFIGURABLE HETEROGENEOUS PROCESSOR ARCHITECTURE WITH LOAD BALANCING AND DYNAMIC ALLOCATION METHOD THEREOF | zh_TW |
| dc.type | Patents | en_US |