Study of board-level noise filters to prevent transient-induced latchup in CMOS integrated circuits during EMC/ESD test

dc.citation.epage	536	en_US
dc.citation.spage	533	en_US
dc.contributor.author	Hsu, Sheng-Fu	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.date.accessioned	2014-12-08T15:25:03Z
dc.date.available	2014-12-08T15:25:03Z
dc.date.issued	2006	en_US
dc.description.abstract	Different types of board-level noise filters are evaluated for their effectiveness to improve the immunity of CMOS ICs against transient-induced latchup (TLU) under system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified in test chips with the silicon controlled rectifier (SCR) fabricated in a 0.25-mu m CMOS technology. Some of such board-level solutions can be further integrated into the chip design to effectively improve TLU immunity of CMOS IC products.	en_US
dc.identifier.isbn	978-3-9522990-3-6	en_US
dc.identifier.journal	2006 17th International Zurich Symposium on Electromagnetic Compatibility, Vols 1 and 2	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/17424
dc.identifier.wosnumber	WOS:000244386300136
dc.language.iso	en_US	en_US
dc.title	Study of board-level noise filters to prevent transient-induced latchup in CMOS integrated circuits during EMC/ESD test	en_US
dc.type	Proceedings Paper	en_US

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