次微米互補式金氧半靜電放電及鎖定之實驗研究及防制

dc.contributor.author	陳明哲	en_US
dc.contributor.author	CHEN MING-JER	en_US
dc.contributor.department	國立交通大學電子工程學系	zh_TW
dc.date.accessioned	2014-12-13T10:38:50Z
dc.date.available	2014-12-13T10:38:50Z
dc.date.issued	1996	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.identifier.govdoc	NSC85-2215-E009-048	zh_TW
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=234622&docId=43069	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/95770
dc.language.iso	zh_TW	en_US
dc.subject	靜電放電	zh_TW
dc.subject	鎖定	zh_TW
dc.subject	基座偏壓產生器	zh_TW
dc.subject	次微米超大型積體電路	zh_TW
dc.subject	ESD	en_US
dc.subject	Latch-up	en_US
dc.subject	Substrate bias generator	en_US
dc.subject	Submicron VLSI	en_US
dc.title	次微米互補式金氧半靜電放電及鎖定之實驗研究及防制	zh_TW
dc.title	Experimental Study and Suppression of ESD/Latch-Up in Submicron CMOS	en_US
dc.type	Plan	en_US

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